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e december 1997 order number: 290207-012 8 n flash electrical chip-erase ? 1 second typical chip-erase n quick-pulse programming algorithm ? 10 s typical byte-program ? 2 second chip-program n 100,000 erase/program cycles n 12.0 v 5% v pp n high-performance read ? 90 ns maximum access time n cmos low power consumption ? 10 ma typical active current ? 50 a typical standby current ? 0 watts data retention power n integrated program/erase stop timer n command register architecture for microprocessor/microcontroller compatible write interface n noise immunity features ? 10% v cc tolerance ? maximum latch-up immunity through epi processing n etox? nonvolatile flash technology ? eprom-compatible process base ? high-volume manufacturing experience n jedec-standard pinouts ? 32-pin plastic dip ? 32-lead plcc ? 32-lead tsop (see packaging spec., order #231369) n extended temperature options intel's 28f010 cmos flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. the 28f010 adds electrical chip-erasure and reprogramming to familiar eprom technology. memory contents can be rewritten: in a test socket; in a prom-programmer socket; on- board during subassembly test; in- system during final test; and in- system after sale. the 28f 010 increases memory flexibility, while contributing to time and cost savings. the 28f010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of eight bits. intel's 28f010 is offered in 32-pin plastic dip or 32-lead plcc and tsop packages. pin assignments conform to jedec standards for byte-wide eproms. extended erase and program cycling capability is designed into intel's etox? (eprom tunnel oxide) process technology. advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional eeproms. with the 12.0 v v pp supply, the 28f010 performs 100,000 erase and program cycleswell within the time limits of the quick-pulse programming and quick-erase algorithms. intel's 28f010 employs advanced cmos circuitry for systems r equiring high-performance access speeds, low power consumption, and immunity to noise. its 90 ns access time provides zero wait-state performance for a wide range of microprocessors and microcontrollers. maximum standby current of 100 a translates into power savings when the device is deselected. finally, the highest degree of latch-up protection is achieved through intel's unique epi processing. prevention of latch-up is provided for stresses up to 100 ma on address and data pins, from C1 v to v cc + 1 v. with intel's etox process technology base, the 28f010 builds on years of eprom experience to yield the highest levels of quality, reliability, and cost-effectiveness. 28f010 1024k (128k x 8) cmos flash memory
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f010 may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1996, 1997. * third-party brands and names are the property of their respective owners.
e 28f010 3 contents page page 1.0 applications ..............................................5 2.0 principles of operation .......................8 2.1 integrated stop timer ..................................8 2.2 write protection ...........................................9 2.2.1 bus operations......................................9 2.2.1.1 read...............................................9 2.2.1.2 output disable ................................9 2.2.1.3 standby ........................................10 2.2.1.4 intelligent identifier operation .......10 2.2.1.5 write .............................................10 2.2.2 command definitions ..........................10 2.2.2.1 read command............................11 2.2.2.2 intelligent identifier command ......11 2.2.2.3 set-up erase/erase commands...12 2.2.2.4 erase verify command.................12 2.2.2.5 set-up program/program commands ..................................12 2.2.2.6 program verify command ............12 2.2.2.7 reset command...........................13 2.2.3 extended erase/program cycling........13 2.2.4 quick-pulse programming algorithm ...13 2.2.5 quick-erase algorithm.........................13 3.0 design considerations ........................16 3.1 two-line output control ............................16 3.2 power supply decoupling ..........................16 3.3 v pp trace on printed circuit boards...........16 3.4 power-up/down protection ........................16 3.5 28f010 power dissipation .........................16 4.0 electrical specifications..................18 4.1 absolute maximum ratings........................18 4.2 operating conditions..................................18 4.3 capacitance ...............................................18 4.4 dc characteristics ttl/nmos compatiblecommercial products...........19 4.5 dc characteristicscmos compatible commercial products ................................20 4.6 dc characteristicsttl/nmos compatibleextended temperature products ....................................................22 4.7 dc characteristicscmos compatible extended temperature products...............23 4.8 ac characteristicsread-only operationscommercial and extended temperature products...............................25 4.9 ac characteristicswrite/erase/program only operations commercial and extended temperature products...............27 4.10 ac characteristicsalternative ce#- controlled writes commercial and extended temperature..............................31 4.11 erase and programming performance......32 5.0 ordering information..........................33 6.0 additional information .......................33
28f010 e 4 revision history number description -007 removed 200 ns speed bin revised erase maximum pulse count for figure 4 from 3000 to 1000 clarified ac and dc test conditions added dimple to f tsop package corrected serpentine layout -008 corrected ac waveforms added extended temperature options -009 added 28f010-65 and 28f010-90 speeds revised symbols, i.e., ce, oe, etc. to ce#, oe#, etc. -010 completion of read operation table labelling of program time in erase/program table textual changes or edits corrected erase/program times -011 minor changes throughout document -012 removed 65 ns speed bin removed tsop package added extended temperature options modified ac test conditions modified ac characteristics
e 28f010 5 1.0 applications the 28f010 flash memory provides nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. these features make the 28f010 an innovative alternative to disk, eeprom, and battery-backed static ram. where periodic updates of code and data tables are required, the 28f010's reprogrammability and nonvolatility make it the obvious and ideal replacement for eprom. primary applications and operating systems stored in flash eliminate the slow disk-to-dram download process. this results in dramatic enhancement of performance and substantial reduction of power consumption a consideration particularly important in portable equipment. flash memory increases flexibility with electrical chip erasure and in- system update capability of operating systems and application code. with updatable code, system manufacturers can easily accommodate last-minute changes as revisions are made. in diskless workstations and terminals, network traffic reduces to a minimum and systems are instant-on. reliability exceeds that of electro- mechanical media. often in these environments, power interruptions force extended re-boot periods for all networked terminals. this mishap is no longer an issue if boot code, operating systems, communication protocols and primary applications are flash resident in each terminal. for embedded systems that rely on dynamic ram/disk for main system memory or nonvolatile backup storage, the 28f010 flash memory offers a solid state alternative in a minimal form factor. the 28f010 provides higher performance, lower power consumption, instant-on capability, and allows an execute in place (xip) memory hierarchy for code and data table reading. additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail. the need for code updates pervades all phases of a system's lifefrom prototyping to system manufacture to after sale service. the electrical chip-erasure and reprogramming ability of the 28f010 allows in-circuit alterability; this eliminates unnecessary handling and less reliable socketed connections, while adding greater test, manufacture, and update flexibility. material and labor costs associated with code changes increases at higher levels of system integrationthe most costly being code updates after sale. code bugs, or the desire to augment system functi onality, prompt after sale code updates. field revisions to eprom-based code requires the removal of eprom components or entire boards. with the 28f010, code updates are implemented locally via an edge connector, or remotely over a communcation link. for systems currently using a high- density static ram/battery configuration for data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. the concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. in addition, flash memory offers a considerable cost advantage over static ram. flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with data accumulation and recording needs. electrical chip-erasure gives the designer a blank slate in which to log or record data. data can be periodically off-loaded for analysis and the flash memory erased producing a new blank slate. a high degree of on-chip feature integration simplifies memory-to-processor interfacing. figure 3 depicts two 28f010s tied to the 80c186 system bus. the 28f010's architecture minimizes interface circuitry needed for complete in-circuit updates of memory contents. the outstanding feature of the tsop (thin small outline package) is the 1.2 mm thickness. tsop is particularly suited for portable equipment and applications requiring large amounts of flash memory. with cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility, the 28f010 offers advantages to the alternatives: eproms, eeproms, battery backed static ram, or disk. eprom-compatible read specifications, straightforward interfacing, and in-circuit alterability offers designers unlimited flexibility to meet the high standards of today's designs.
28f010 e 6 290207-1 figure 1. 28f010 block diagram table 1. pin description symbol type name and function a 0 Ca 16 input address inputs for memory addresses. addresses are internally latched during a write cycle. dq 0 Cdq 7 input/output data input/output: inputs data during memory write cycles; outputs data during memory read cycles. the data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. data is internally latched during a write cycle ce# input chip enable: activates the device's control logic, input buffers, decoders and sense amplifiers. ce# is active low; ce# high deselects the memory device and reduces power consumption to standby levels. oe# input output enable: gates the devices output through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the control register and the array. write enable is active low. addresses are latched on the falling edge and data is latched on the rising edge of the we# pulse. note: with v pp 6.5 v, memory contents cannot be altered.
e 28f010 7 table 1. pin description (continued) symbol type name and function v pp erase/program power supply for writing the command register, erasing the entire array, or programming bytes in the array. v cc device power supply (5 v 10%) v ss ground nc no internal connection to device. pin may be driven or left floating. figure 2. 28f010 pin configurations
28f010 e 8 290207-4 figure 3. 28f010 in a 80c186 system 2.0 principles of operation flash memory augments eprom functionality with in-circuit electrical erasure and reprogramming. the 28f010 introduces a command register to manage this new functionality. the command register allows for: 100% ttl-level control inputs; fixed power supplies during erasure and programming; and maximum eprom compatibility. in the absence of high voltage on the v pp pin, the 28f010 is a read-only memory. manipulation of the external memory control pins yields the standard eprom read, standby, output disable, and intelligent identifier operations. the same eprom read, standby, and output disable operations are available when high voltage is applied to the v pp pin. in addition, high voltage on v pp enables erasure and programming of the device. all functions associated with altering memory contents intelligent identifier, erase, erase verify, program, and program verifyare accessed via the command register. commands are written to the register using standard microprocessor write timings. register contents serve as input to an internal state machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for programming or erase operations. with the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output data for erase and program verification. 2.1 integrated stop timer successive command write cycles define the durations of program and erase operations; specifically, the program or erase time durations are normally terminated by associated program or erase verify commands. an integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing specifications. programming and erase pulse durations are minimums only. when the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.
e 28f010 9 table 2. 28f010 bus operations mode v pp (1) a 0 a 9 ce# oe# we# dq 0 Cdq 7 read v ppl a 0 a 9 v il v il v ih data out output disable v ppl xxv il v ih v ih tri-state read-only standby v ppl xxv ih x x tri-state intelligent identifier (mfr) (2) v ppl v il v id (3) v il v il v ih data = 89h intelligent identifier (device) (2) v ppl v ih v id (3) v il v il v ih data = b4h read v pph a 0 a 9 v il v il v ih data out (4) read/write output disable v pph xxv il v ih v ih tri-state standby (5) v pph xxv ih x x tri-state write v pph a 0 a 9 v il v ih v il data in (6) notes: 1. refer to dc characteristics . when v pp = v ppl memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 3. all other addresses low. 3. v id is the intelligent identifier high voltage. refer to dc characteristics . 4. read operations with v pp = v pph may access array data or the intelligent identifier codes. 5. with v pp at high voltage, the standby current equals i cc + i pp (standby). 6. refer to table 3 for valid data-in during a write operation. 7. x can be v il or v ih . 2.2 write protection the command register is only active when v pp is at high voltage. depending upon the application, the system desi gner may choose to make the v pp power supply switchable available only when memory updates are desired. when v pp = v ppl , the contents of the register default to the read command, making the 28f010 a read-only memory. in this mode, the memory contents cannot be altered. or, the system desi gner may choose to hardwire v pp , making the high voltage supply constantly available. in this case, all command register functions are inhibited whenever v cc is below the write lockout voltage v lko . (see section 3.4, power-up/down protection .) the 28f010 is designed to accommodate either design practice, and to encourage optimization of the processor memory interface. the two-step program/erase write sequence to the command register provides additional software write protections. 2.2.1 bus operations 2.2.1.1 read the 28f010 has two control functions, both of which must be logically active, to obtain data at the outputs. chip enable (ce#) is the power control and should be used for device selection. output enable (oe#) is the output control and should be used to gate data from the output pins, independent of device selection. refer to the ac read timing waveforms. when v pp is high (v pph ), the read operation can be used to access array data, to output the intelligent identifier codes, and to access data for program/erase verification. when v pp is low (v ppl ), the read operation can only access the array data. 2.2.1.2 output disable with oe# at a logic-high level (v ih ), output from the device is disabled. output pins are placed in a high- impedance state.
28f010 e 10 2.2.1.3 standby with ce# at a logic-high level, the standby operation disables most of the 28f010s circuitry and substantially reduces device power consumption. the outputs are placed in a high- impedance state, independent of the oe# signal. if the 28f010 is deselected during erasure, programming, or program/erase verification, the device draws active current until the operation is terminated. 2.2.1.4 intelligent identifier operation the intelligent identifier operation outputs the manufacturer code (89h) and device code (b4h). programming equipment automatically matches the device with its proper erase and programming algorithms. with ce# and oe# at a logic low level, raising a 9 to high voltage v id (see dc characteristics ) activates the operation. data read from locations 0000h and 0001h represent the manufacturer's code and the device code, respectively. the manufacturer and device codes can also be read via the command register, for instances where the 28f010 is erased and reprogrammed in the target system. following a write of 90h to the command register, a read from address location 0000h outputs the manufacturer code (89h). a read from address 0001h outputs the device code (b4h). 2.2.1.5 write device erasure and programming are accomplished via the command register, when high voltage is applied to the v pp pin. the contents of the register serve as input to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy an addressable memory location. the register is a latch used to store the command, along with address and data information needed to execute the command. the command register is written by bringing we# to a logic-low level (v il ), while ce# is low. addresses are latched on the falling edge of we#, while data is latched on the rising edge of the we# pulse. standard microprocessor write timings are used. refer to ac characteristics write/erase/program only operations and the erase/programming waveforms for specific timing parameters. 2.2.2 command definitions when low voltage is applied to the v pp pin, the contents of the command register default to 00h, enabling read-only operations. placing high voltage on the v pp pin enables read/write operations. device operations are selected by writing specific data patterns into the command register. table 3 defines these 28f010 register commands.
e 28f010 11 table 3. command definitions first bus cycle second bus cycle command bus cycles req'd operation (1) address (2) data (3) operation (1) address (2) data (3) read memory 1 write x 00h read intelligent identifier codes (4) 3 write ia 90h read ia id set-up erase/erase (5) 2 write x 20h write x 20h erase verify (5) 2 write ea a0h read x evd set-up program/ program (6) 2 write x 40h write pa pd program verify (6) 2 write x c0h read x pvd reset (7) 2 write x ffh write x ffh notes: 1. bus operations are defined in table 2. 2. ia = identifier address: 00h for manufacturer code, 01h for device code. ea = erase address: address of memory location to be read during erase verify. pa = program address: address of memory location to be programmed. addresses are latched on the falling edge of the we# pulse. 3. id = identifier data: data read from location ia during device identification (mfr = 89h, device = b4h). evd = erase verify data: data read from location ea during erase verify. pd = program data: data to be programmed at location pa. data is latched on the rising edge of we#. pvd = program verify data: data read from location pa during program verify. pa is latched on the program command. 4. following the read intelligent id command, two read operations access manufacturer and device codes. 5. figure 5 illustrates the 28f010 quick-erase algorithm flowchart. 6. figure 4 illustrates the 28f010 quick-pulse programming algorithm flowchart. 7. the second bus cycle must be followed by the desired command register write. 2.2.2.1 read command while v pp is high, for erasure and programming, memory contents can be accessed via the read command. the read operation is initiated by writing 00h into the command register. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register contents are altered. the default contents of the register upon v pp power-up is 00h. this default value ensures that no spurious alteration of memory contents occurs during the v pp power transition. where the v pp supply is hardwired to the 28f010, the device powers-up and remains enabled for reads until the command register contents are changed. refer to the ac characteristics read-only operations and waveforms for specific timing parameters. 2.2.2.2 intelligent identifier command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be accessible while the device resides in the target system. prom programmers typically access signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto address lines is not a desired system design practice. the 28f010 contains an intelligent identifier operation to supplement traditional prom- programming methodology. the operation is initiated by writing 90h into the command register. following the command write, a read cycle from address 0000h retrieves the manufacturer code of 89h. a read cycle from address 0001h returns the device code of b4h. to terminate the operation, it
28f010 e 12 is necessary to write another valid command into the register. 2.2.2.3 set-up erase/erase commands set-up erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. the set-up erase operation is performed by writing 20h to the command register. to commence chip-erasure, the erase command (20h) must again be written to the register. the erase operation begins with the rising edge of the we# pulse and terminates with the rising edge of the next we# pulse (i.e., erase verify command). this two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. also, chip-erasure can only occur when high voltage is applied to the pin. in the absence of this high voltage, memory contents are protected against erasure. refer to ac characteristics write/erase/program only oper- ations and waveforms for specific timing parameters. 2.2.2.4 erase verify command the erase command erases all bytes of the array in parallel. after each erase operation, all bytes must be verified. the erase verify operation is initiated by writing a0h into the command register. the address for the byte to be verified must be supplied as it is latched on the falling edge of the we# pulse. the register write terminates the erase operation with the rising edge of its we# pulse. the 28f010 applies an internally-generated margin voltage to the addressed byte. reading ffh from the addressed byte indicates that all bits in the byte are erased. the erase verify command must be written to the command register prior to each byte verification to latch its address. the process continues for each byte in the array until a byte does not return ffh data, or the last address is accessed. in the case where the data read is not ffh, another erase operation is performed. (refer section 2.2.2.3, set-up erase/erase commands. ) verification then resumes from the address of the last-verified byte. once all bytes in the array have been verified, the erase step is complete. the device can be programmed. at this point, the verify operation is terminated by writing a valid command (e.g., program set-up) to the command register. figure 5, the 28f010 quick- erase algorithm flowchart, illustrates how commands and bus operations are combined to perform electrical erasure of the 28f010. refer to ac characteristicswrite/erase/program only operations and waveforms for specific timing parameters. 2.2.2.5 set-up program/program commands set-up program is a command-only operation that stages the device for byte programming. writing 40h into the command register performs the set-up operation. once the program set-up operation is performed, the next we# pulse causes a transition to an active programming operation. addresses are internally latched on the falling edge of the we# pulse. data is internally latched on the rising edge of the we# pulse. the rising edge of we# also begins the programming operation. the programming operation terminates with the next rising edge of we#, used to write the program verify command. refer to ac characteristicswrite/erase/program only operations and waveforms for specific timing parameters. 2.2.2.6 program verify command the 28f010 is programmed on a byte-by-byte basis. byte programming may occur sequentially or at random. following each programming operation, the byte just programmed must be verified. the program verify operation is initiated by writing c0h into the command register. the register write terminates the programming operation with the rising edge of its we# pulse. the program verify operation stages the device for verification of the byte last programmed. no new address information is latched. the 28f010 applies an internally-generated margin voltage to the byte. a microprocessor read cycle outputs the data. a successful comparison between the programmed byte and true data means that the byte is successfully programmed. programming then proceeds to the next desired byte location. figure 5, the 28f010 quick-pulse programming algorithm flowchart, illustrates how commands are combined with bus operations to perform byte
e 28f010 13 programming. refer to ac characteristics write/erase/program only operations and waveforms for specific timing parameters. 2.2.2.7 reset command a reset command is provided as a means to safely abort the erase or program command sequences. following either set-up command (erase or program) with two consecutive writes of ffh will safely abort the operation. memory contents will not be altered. a valid command must then be written to place the device in the desired state. 2.2.3 extended erase/program cycling eeprom cycling failures have always concerned users. the high electrical field required by thin oxide eeproms for tunneling can literally tear apart the oxide at defect regions. to combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. however, redundancy requires that cell size be doubled an expensive solution. intel has designed extended cycling capability into its etox flash memory technology. resulting improvements in cycling reliability come without increasing memory cell size or complexity. first, an advanced tunnel oxide increases the charge carrying ability ten-fold. second, the oxide area per cell subjected to the tunneling electric field is one- tenth that of common eeproms, minimizing the probability of oxide defects in the region. finally, the peak electric field during erasure is approximately 2 mv/cm lower than eeprom. the lower electric field greatly reduces oxide stress and the probability of failure. the 28f010 is capable or 100,000 program/erase cycles. the device is programmed and erased using intel's quick-pulse programming and quick- erase algorithms. intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program the device. 2.2.4 quick-pulse programming algorithm the quick-pulse programming algorithm uses programming operations of 10 s duration. each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. the algorithm allows for up to 25 programming operations per byte, although most bytes verify on the first or second operation. the entire sequence of programming and byte verification is performed with v pp at high voltage. figure 4 illustrates the 28f010 quick-pulse programming algorithm flowchart. 2.2.5 quick-erase algorithm intel's quick-erase algorithm yields fast and reliable electrical erasure of memory contents. the algorithm employs a closed-loop flow, similar to the quick-pulse programming algorithm, to simul- taneously remove charge from all bits in the array. erasure begins with a read of memory contents. the 28f010 is erased when shipped from the factory. reading ffh data from the device would immediately be followed by device programming. for devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (data = 00h). this is accomplished, using the quick-pulse programming algorithm, in approxi- mately two seconds. erase execution then continues with an initial erase operation. erase verification (data = ffh) begins at address 0000h and continues through the array to the last address, or until data other than ffh is encountered. with each erase operation, an increasing number of bytes verify to the erased state. erase efficiency may be improved by storing the address of the last byte verified in a register. following the next erase operation, verification starts at that stored address location. erasure typically occurs in one second. figure 5 illustrates the 28f010 quick-erase algorithm flowchart.
28f010 e 14 start programming (4) apply v pph (1) plscnt = 0 write set-up program cmd write program verify cmd read data from device write read cmd verify data inc plscnt =25? last address? programming completed program error write program cmd (a/d) time out 10 s apply v ppl (1) apply v ppl (1) time out 6 s increment address n bus operation command comments initialize pulse-count write set-up program data = 40h write program valid address/data standby duration of program operation (t whwh1 ) write program verify (2) data = c0h; stops program operations (3) stand-by t whgl read read byte to verify programming standby wait for v pp ramp to v pph (1) standby compare data output to data expected standby wait for v pp ramp to v ppl (1) write read data = 00h, resets the register for read operations y n y y n 0207_04 notes: 1. see dc characteristics for the value of v pph and v ppl . 2. program verify is only performed after byte programming. a final read/compare may be performed (optional) after the register is written with the read command. 3. refer to principles of operation . 4. caution: the algorithm must be followed to ensure proper and reliable operation of the device. figure 4. 28f010 quick-pulse programming algorithm
e 28f010 15 start erasure (4) data = 00h? program all bytes to 00h apply v pph (1) addr = 00h plscnt = 0 time out 10 ms time out 6 s read data from device data = ffh? inc plscnt = 1000? last address? erasure completed erase error write erase set-up cmd write erase cmd write read cmd apply v ppl (1) apply v ppl (1) write erase verify cmd increment addr y bus operation comments entire memory must = 00h before erasure use quick-pulse programming algorithm (figure 4) standby wait for v pp ramp to v pph (1) initialize addresses and pulse-count write data = 20h write data = 20h stand-by duration of erase operation (t whwh2 ) write addr = byte to verify; data = a0h; stops erase operation (3) standby t whgl read read byte to verify erasure standby compare output to ffh increment pulse-count standby wait for v pp ramp to v ppl (1) n y n n n y y command set-up erase erase erase (2) verify write data = 00h, resets the register for read operations read 0207_05 notes: 1. see dc characteristics for the value of v pph and v ppl . 2. erase verify is performed only after chip-erasure. a final read/compare may be performed (optional) after the register is written with the read command. 3. refer to principles of operation . 4. caution: the algorithm must be followed to ensure proper and reliable operation of the device. figure 5. 28f010 quick-erase algorithm
28f010 e 16 3.0 design considerations 3.1 two-line output control flash memories are often used in larger memory arrays. intel provides two read control inputs to accommodate multiple memory connections. two- line control provides for: a. the lowest possible memory power dissipation and, b. complete assurance that output bus contention will not occur. to efficiently use these two control inputs, an address decoder output should drive chip-enable, while the system's r ead signal controls all flash memories and other parallel memories. this assures that only enabled memory devices have active outputs, while deselected devices maintain the low power standby condition. 3.2 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current (i cc ) issues standby, active, and transient current peaks produced by falling and rising edges of chip- enable. the capacitive and inductive loads on the device outputs determine the magnitudes of these peaks. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between v cc and v ss , and between v pp and v ss . place the high-frequency, low-inherent inductance capacitors as close as possible to the devices. also, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the array's power supply connection, between v cc and v ss . the bulk capacitor will overcome voltage slumps caused by printed circuit board trace inductance, and will supply charge to the smaller capacitors as needed. 3.3 v pp trace on printed circuit boards programming flash memories, while they reside in the target system, r equires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for programming. use similar trace widths and layout considerations given the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 3.4 power-up/down protection the 28f010 is designed to offer protection against accidental erasure or programming during power transitions. upon power-up, the 28f010 is indifferent as to which power supply, v pp or v cc , powers up first. power supply sequencing is not required. internal circuitry in the 28f010 ensures that the command register is reset to the read mode on power-up. a system desi gner must guard against active writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the control register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. 3.5 28f010 power dissipation when designing portable systems, desi gners must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash nonvolatility increases the usable battery life of your system because the 28f010 does not consume any power to retain code or data when the system is off. table 4 illustrates the power dissipated when updating the 28f010.
e 28f010 17 table 4. 28f010 typical update power dissipation (4) operation notes power dissipation (watt-seconds) array program/program verify 1 0.171 array erase/erase verify 2 0.136 one complete cycle 3 0.478 notes: 1. formula to calculate typical program/program verify power = [v pp # bytes typical # prog pulses (t whwh1 i pp2 typical + t whgl i pp4 typical)] + [v cc # bytes typical # prog pulses (t whwh1 i cc2 typical + t whgl i cc4 typical]. 2. formula to calculate typical erase/erase verify power = [v pp (v pp3 typical t erase typical + i pp5 typical t whgl # bytes)] + [v cc (i cc3 typical t erase typical + i cc5 typical t whgl # bytes)]. 3. one complete cycle = array preprogram + array erase + program. 4. typicals are not guaranteed, but based on a limited number of samples from production lots.
28f010 e 18 4.0 electrical specifications 4.1 absolute maximum ratings* operating temperature during read ............................... 0 c to +70 c (1) during erase/program................0 c to +70 c (1) operating temperature during read ...........................C40 c to +85 c (2) during erase/program............C40 c to +85 c (2) temperature under bias............C10 c to +80 c (1) temperature under bias............C50 c to +95 c (2) storage temperature.................. C65 c to +125 c voltage on any pin with respect to ground .................. C2.0 v to +7.0 v (3) voltage on pin a 9 with respect to ground ............. C2.0 v to +13.5 v (3, 4) v pp supply voltage with respect to ground during erase/program........ C2.0 v to +14.0 v (3, 4) v cc supply voltage with respect to ground .................. C2.0 v to +7.0 v (3) output short circuit current..................... 100 ma (5) notice: this is a production datasheet. the specifications are subject to change without notice. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. notes: 1. operating temperature is for commercial product as defined by this specification. 2. operating temperature is for extended temperature products as defined by this specification. 3. minimum dc input voltage is C0.5 v. during transitions, inputs may undershoot to C2.0 v for periods less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods less than 20 ns. 4. maximum dc voltage on a 9 or v pp may overshoot to +14.0 v for periods less than 20 ns. 5. output shorted for no more than one second. no more than one output shorted at a time. 6. see ac testing input/output waveform (figure 6) and ac testing load circuit (figure 7) for testing characteristics. 4.2 operating conditions limits symbol parameter min max unit t a operating temperature (1) 070 c t a operating temperature (2) C40 +85 c v cc v cc supply voltage (10%) (6) 4.50 5.50 v v cc v cc supply voltage (5%) (7) 4.75 5.25 v 4.3 capacitance t a = 25 c, f = 1.0 mhz limits symbol parameter notes min max unit conditions c in address/control capacitance 1 8 pf v in = 0 v c out output capacitance 1 12 pf v out = 0 v note: 1. sampled, not 100% tested.
e 28f010 19 4.4 dc characteristics ttl/nmos compatiblecommercial products limits symbol parameter notes min typ (3) max unit test conditions i li input leakage current 1 1.0 a v cc = v cc max v in = v cc or v ss i lo output leakage current 1 10 a v cc = v cc max v out = v cc or v ss i ccs v cc standby current 1 0.3 1.0 ma v cc = v cc max ce# = v ih i cc1 v cc active read current 1 10 30 ma v cc = v cc max, ce# = v il f = 6 mhz, i out = 0 ma i cc2 v cc programming current 1, 2 1.0 10 ma programming in progress i cc3 v cc erase current 1, 2 5.0 15 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 15 ma v pp = v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 15 ma v pp = v pph erase verify in progress i pps v pp leakage current 1 10 a v pp v cc i pp1 v pp read current or standby current 1 90 200 a v pp > v cc 10.0 v pp v cc i pp2 v pp programming current 1, 2 8.0 30 ma v pp = v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp = v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp = v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp = v pph erase verify in progress v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 2.4 v v cc = v cc min i oh = C2.5 ma v id a 9 intelligent identifier voltage 11.50 13.00 v
28f010 e 20 4.4 dc characteristics ttl/nmos compatiblecommercial products (continued) limits symbol parameter notes min typ (3) max unit test conditions i id a 9 intelligent identifier current 1, 2 90 200 a a 9 = v id v ppl v pp during read-only operations 0.00 6.5 v note: erase/program are inhibited when v pp = v ppl v pph v pp during read/write operations 11.40 12.60 v v lko v cc erase/write lock voltage 2.5 v notes: sampled, not 100% tested. 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, v pp = 12.0 v, t = 25 c. these currents are valid for all product versions (packages and speeds). 2. not 100% tested: characterization data available. 3. typicals are not guaranteed, but based on a limited number of samples from production lots. 4.5 dc characteristics cmos compatiblecommercial products limits symbol parameter notes min typ (3) max unit test conditions i li input leakage current 1 1.0 a v cc = v cc max v in = v cc or v ss i lo output leakage current 1 10 a v cc = v cc max v out = v cc or v ss i ccs v cc standby current 1 50 100 a v cc = v cc max ce# = v cc 0.2 v i cc1 v cc active read current 1 10 30 ma v cc = v cc max, ce# = v il f = 6 mhz, i out = 0 ma i cc2 v cc programming current 1, 2 1.0 10 ma programming in progress i cc3 v cc erase current 1, 2 5.0 15 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 15 ma v pp = v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 15 ma v pp = v pph erase verify in progress i pps v pp leakage current 1 10 a v pp v cc
e 28f010 21 4.5 dc characteristics cmos compatiblecommercial products (continued) limits symbol parameter notes min typ (3) max unit test conditions i pp1 v pp read current, id current or standby current 1 90 200 a v pp > v cc 10 v pp v cc i pp2 v pp programming current 1, 2 8.0 30 ma v pp > = v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp = v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp = v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp = v pph erase verify in progress v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh2 v cc C 0.4 v cc = v cc min i oh = C100 a v id a 9 intelligent identifier voltage 11.50 13.00 v i id a 9 intelligent identifier current 1, 2 90 200 a a 9 = v id v ppl v pp during read-only operations 0.00 6.5 v note: erase/programs are inhibited when v pp = v ppl v pph v pp during read/write operations 11.40 12.60 v v lko v cc erase/write lock voltage 2.5 v notes: refer to section 4.4.
28f010 e 22 4.6 dc characteristics ttl/nmos compatibleextended temperature products limits symbol parameter notes min typ (3) max unit test conditions i li input leakage current 1 1.0 a v cc = v cc max v in = v cc or v ss i lo output leakage current 1 10 a v cc = v cc max v out = v cc or v ss i ccs v cc standby current 1 0.3 1.0 ma v cc = v cc max ce# = v ih i cc1 v cc active read current 1 10 30 ma v cc = v cc max, ce# = v il f = 6 mhz, i out = 0 ma i cc2 v cc programming current 1, 2 1.0 30 ma programming in progress i cc3 v cc erase current 1, 2 5.0 30 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 30 ma v pp = v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 30 ma v pp = v pph erase verify in progress i pps v pp leakage current 1 10 a v pp v cc i pp1 v pp read current or standby current 1 90 200 a v pp > v cc 10.0 v pp v cc i pp2 v pp programming current 1, 2 8.0 30 ma v pp = v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp = v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp = v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp = v pph erase verify in progress v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 2.4 v v cc = v cc min i oh = C2.5 ma v id a 9 intelligent identifier voltage 11.50 13.00 v
e 28f010 23 4.6 dc characteristics ttl/nmos compatibleextended temperature products (continued) limits symbol parameter notes min typ (3) max unit test conditions i id a 9 intelligent identifier current 1, 2 90 500 a a 9 = v id v ppl v pp during read-only operations 0.00 6.5 v note: erase/program are inhibited when v pp = v ppl v pph v pp during read/write operations 11.40 12.60 v v lko v cc erase/write lock voltage 2.5 v notes: refer to section 4.4. 4.7 dc characteristics cmos compatibleextended temperature products limits symbol parameter notes min typ (3) max unit test conditions i li input leakage current 1 1.0 a v cc = v cc max v in = v cc or v ss i lo output leakage current 1 10 a v cc = v cc max v out = v cc or v ss i ccs v cc standby current 1 50 100 a v cc = v cc max ce# = v cc 0.2 v i cc1 v cc active read current 1 10 30 ma v cc = v cc max, ce# = v il f = 10 mhz, i out = 0 ma i cc2 v cc programming current 1, 2 1.0 10 ma programming in progress i cc3 v cc erase current 1, 2 5.0 30 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 30 ma v pp = v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 30 ma v pp = v pph erase verify in progress i pps v pp leakage current 1 10 a v pp v cc i pp1 v pp read current, id current or standby current 1 90 200 a v pp > v cc 10 v pp v cc
28f010 e 24 4.7 dc characteristics cmos compatibleextended temperature products (continued) limits symbol parameter notes min typ (3) max unit test conditions i pp2 v pp programming current 1, 2 8.0 30 ma v pp = v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp = v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp = v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp = v pph erase verify in progress v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh2 v cc C 0.4 v cc = v cc min i oh = C100 a v id a 9 intelligent identifier voltage 11.50 13.00 v i id a 9 intelligent identifier current 1, 2 90 500 a a 9 = v id v ppl v pp during read-only operations 0.00 6.5 v note: erase/programs are inhibited when v pp = v ppl v pph v pp during read/write operations 11.40 12.60 v v lko v cc erase/write lock voltage 2.5 v note: refer to section 4.4.
e 28f010 25 output test points input 2.0 0.8 2.0 0.8 2.4 0.45 0207_06 ac test inputs are driven at v oh (2.4 v ttl ) for a logic 1 and v ol (0.45 v ttl ) for a logic 0. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. figure 6. testing input/output waveform (1) note: 1. testing characteristics for 28f010-90, 28f010-120, and 28f010-150. device under test out r l = 3.3 k w 1n914 1.3v c l = 100 pf 0207_07 c l includes jig capacitance figure 7. ac testing load circuit 4.8 ac characteristics read-only operationscommercial and extended temperature products versions 28f010-90 (1) 28f010-120 (1) 28f010-150 (1) symbol characteristic notes min max min max min max unit t avav /t rc read cycle time 90 120 150 ns t elqv /t ce ce# access time 90 120 150 ns t avqv /t acc address access time 90 120 150 ns t glqv /t oe oe# access time 35 50 55 ns t elqx /t lz ce# to low z 2, 3 0 0 0 ns t ehqz chip disable to output in high z 2 455555ns t glqx /t olz oe# to output in low z 2, 3 0 0 0 ns t ghqz /t df output disable to output in high z 2 303035ns t oh output hold from address, ce#, or oe# change 2, 4 0 0 0 ns t whgl write recovery time before read 666 s notes: 1. see ac input/output waveform and ac testing load circuit for testing characteristics. 2. sampled, not 100% tested. 3. guaranteed by design. 4. whichever occurs first.
28f010 e 26 290207-9 figure 8. ac waveforms for read operations
e 28f010 27 4.9 ac characteristics write/erase/program only operations (1) commercial and extended temperature products versions 28f010-90 (2) 28f010-120 (2) 28f010-150 (2) symbol characteristic notes min max min max min max unit t avav /t wc write cycle time 90 120 150 ns t avwl /t as address set-up time 0 0 0 ns t wlax /t ah address hold time 40 40 40 ns 355 t dvwh /t ds data set-up time 40 40 40 ns 55 t whdx /t dh data hold time 10 10 10 ns t whgl write recovery time before read 666 s t ghwl read recovery time before write 4000ns t elwl /t cs chip enable set-up time before write 15 15 15 ns t wheh /t ch chip enable hold time 0 0 0 ns t wlwh /t wp write pulse width 40 60 60 ns 355 t whwl /t wph write pulse width high 20 20 20 ns t whwh1 duration of programming operation 5101010s t whwh2 duration of erase operation 5 9.5 9.5 9.5 ms t vpel v pp set-up time to chip enable low 4111s notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read-only operations . 2. see ac input/output waveform and ac testing load circuit for testing characteristics. 3. minimum specification for extended temperature product. 4. guaranteed by design. 5. the integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
28f010 e 28 290207-13 figure 9. typical programming capability 290207-14 figure 10. typical program time at 12 v 290207-15 figure 11. typical erase capability 290207-16 figure 12. typical erase time at 12 v
e 28f010 29 290207-10 figure 13. ac waveforms for programming operations
28f010 e 30 290207-11 figure 14. ac waveforms for erase operations
e 28f010 31 4.10 ac characteristics alternative ce#-controlled writes (1) commercial and extended temperature versions 28f010-90 (2) 28f010-120 (2) 28f010-150 (2) symbol characteristic notes min max min max min max unit t avav write cycle time 90 120 150 ns t avel address set-up time 0 0 0 ns t elax address hold time 45 55 55 ns 360 t dveh data set-up time 35 45 45 ns 350 t ehdx data hold time 10 10 10 ns t ehgl write recovery time before read 666 s t ghwl read recovery time before write 4000ns t wlel write enable set-up time before chip enable 000ns t ehwh write enable hold time 0 0 0 ns t eleh write pulse width 45 70 70 ns 360 t ehel write pulse width high 20 20 20 ns t eheh1 duration of programming operation 5101010s t eheh2 duration of erase operation 5 9.5 9.5 9.5 ms t vpel v pp set-up time to chip enable low 4111s notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read-only operations . 2. see ac input/output waveform and ac testing load circuit for testing characteristics. 3. minimum specification for extended temperature product. 4. guaranteed by design. 5. the integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
28f010 e 32 4.11 erase and programming performance parameter notes min typical max unit chip erase time 1, 3, 4 1 10 sec chip program time 1, 2, 4 2 12.5 sec notes: 1. typicals are not guaranteed, but based on samples from production lots. data taken at 25 c, 12.0 v v pp . 2. minimum byte programming time excluding system overhead is 16 sec (10 sec program + 6 sec write recovery), while maximum is 400 sec/byte (16 sec x 25 loops allowed by algorithm). max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. excludes 00h programming prior to erasure. 4. excludes system level overhead. 290207-19 note: alternative ce#-controlled write timings also apply to erase operations. figure 15. alternate ac waveforms for programming operations
e 28f010 33 5.0 ordering information e 2 8 f 0 1 0 - 1 2 0 operating temperature t = extended temp blank = commercial temp access speed (ns) valid combinations: e28f010-90 n28f010-90 p28f010-90 e28f010-120 n28f010-120 p28f010-120 e28f010-150 n28f010-150 p28f010-150 te28f010-90 tn28f010-90 TP28F010-90 te28f010-120 tn28f010-120 tp28f010-120 te28f010-150 tn28f010-150 tp28f010-150 package p = 32-pin pdip n = 32-lead plcc e = 32-lead tsop density 010 = 1 mbit product line designator for all intel flash products 290207-20 6.0 additional information visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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